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Spurs in the output signal of AD9516-1

Question asked by alex987 on Apr 24, 2017
Latest reply on Apr 27, 2017 by Clarence.Mayott

Hello
I use AD9516-1 to get the frequencies 1205, 602.5, 302.5 MHz and others.
The reference frequency is 10 MHz.
At the output of the signal, I see the spurs of a large level with the detuning of 48-49 kHz.

The VCO is used internally. In the reference signal, the spurs are absent.
I fed the reference signal from another source, changed the parameters of the LOOP filter - the spurs did not change.
Whether there can be a problem in loading of registers?
I ship in such sequence

 


Adr   Data
0x00  0x99    // SDO active
0x10  0x7C    // PLL operation Mode: Normal operation
0x11  0x02    // R divider: 2
0x13  0x02    // A counter: 2
0x14  0x1E    // B counter: 30
0x15  0x00    // B counter MSB = 0
0x16  0x05    // Prescaler P=16/17
0x17  0x84    // Status pin control: REF 1 clock on status pin
0x18  0x06    // PLL control 0bit - CAL VCO
0x232 0x01    // Update all registers

0x1C  0x01    // Differential reference: differential reference mode
0x140 0x42    // 6 - LVDS
0x141 0x42    //  7 - LVDS
0x142 0x42    //  8 - LVDS
0x143 0x42    //  9 - LVDS    
0x190 0x00
0x191 0x80    //  bypass  div2
0x192 0x00
0x193 0x00
0x194 0x00
0x195 0x00
0x196 0x11
0x197 0x00
0x198 0x00
0x199 0xFF
0x19A 0x00
0x19B 0x11
0x19C 0x00
0x19D 0x00
0x19E 0x11
0x19F 0x00
0x1A0 0x00
0x1A1 0x00
0x1A2 0x00
0x1E0 0x00
0x1E1 0x02 // Select VCO or CLK: Selects VCO as input to VCO divider;

0x232 0x01 // Update all registers

 

Thank you

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