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fmcomms2/zed timing failure

Question asked by PFL on Apr 24, 2017
Latest reply on Apr 25, 2017 by PFL



I'm using the HDL reference design fmcomms2 for Zedboard as basis for a transceiver development.

I have an issue whereby when I add my own IP, various paths in the original reference design fail timing; specifically the the HDMI core and rx_clock in rx channel3.  So I tried locking some P&R.  Having failed to achieve the desired effect locking various portions using pblocks, I decided to see what the tcl command lock_design would do.  So with a fresh build of 2016_r2, using the recommended Vivado 2016.2, I ran lock_design on the untouched reference design.  I then ran implementation again, and found that the timing constraints weren't  met.  Nothing in the reference design had been touched, it has simply been locked immediately after building with "make fmcomms2.zed" under cygwin.  


The design builds in it's "implemented" state, with all constraints met.  Why doesn't lock_design preserve this when implementation is run again without making any changes?  I guess I have to be doing something wrong or misunderstanding something here.