My issue comes from that ADC output between successive measurements is inconsistent. The ADC is sending out information on DATA - 13 while simultaneously sending pulses on the BUSY - 17 line. Also, the BUSY data pulse is not always synchronous with the SYNC - 11. I believe the improper send/receive of the BUSY line is also causing the subsequent cycle output of the ADC to be improperly formatted and thus the conversion from DATA - 13 may be erroneous.I am currently using an AD977CNZ ADC (ADC) as an analog signal acquisition tool and I am unsure of why there are variations between cycles on the ADC. I currently have the ADC set to +/- 3.333 V range; SB/BTC - 8 set to logic LOW; EXT/INT - set to logic HIGH; and CS - 16 set to logic LOW, with the intention of retrieving data as shown by the scheme in Figure 6 from the support pdf ( http://www.analog.com/media/en/technical-documentation/data-sheets/AD977_977A.pdf ) while using a digital waveform generator with a clock cycle set to 5 Hz - 50% duty cycle to generate pulses.
What needs to be done to correct this?