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AD7091R-2 dual channels converting  issue

Question asked by Verti on Apr 20, 2017
Latest reply on Apr 21, 2017 by Gnib

Dear Specialists,

         Now we use AD7091R-2 dual channels in design. We follow the reference code and Channel 1 can run OK but can not get right output data from channel 2. So we try to slow down the converting time step by step, when the converting time extend to 312.5us, it works well when only read one channel's date after a complete converting,below are the related code FYR.

It's a fast ADC in spec,can you kindly give you advice, thank you.

 

 

==================================================

void TIM3_IRQHandler(void)   //312.5us

{

if ( TIM_GetITStatus(TIM3 , TIM_IT_Update) != RESET )

{

TIM_ClearITPendingBit(TIM3 , TIM_FLAG_Update);

Single_Read_All_Data();

   }

}

 

//can only read one channel's data after a complete converting, otherwise only output right data in channel 1 . 

uint16_t Single_Read_All_Data(void)

{

uint16_t Config=0,DataConfig,d1,d2;

// Config=(CHN|CH0_EN);

//Config=CH_ALL_DIS|CH0_EN;

 

// WriteRegister(Config,2);

  WriteRegister(0,2);

DataConfig =  (uint16_t)InputBuf[0];

DataConfig <<= 8;

DataConfig |= (uint16_t)InputBuf[1];

ChData[0] = DataConfig;

ConvStart();

if ((ChData[0] & 0xe000)==0)

{

AD1[pint1]=ChData[0] & 0x0fff; //output voltage

    FAD1[pint1]=AD1[pint1]*AD1[pint1];

    pint1++;

}

else

{

AD2[pint2]=ChData[0] & 0x0fff;//output voltage

    FAD2[pint2]=AD2[pint2]*AD2[pint2];

    pint2++;

}

pint1=pint1 % 32; pint2=pint2 % 32;

pint++;

return *ChData;

}

 

 initializer

oid R7091R2InI(void)

{

SoftwareReset();

Delay(20);

Wr_Config_AD7091R(0x0c01);//CLR_ALRT_RD|ALRT_DRV_CMOS|PDOWN_MODE_0);   // Configures the AD7091R

// Wr_Chn_Reg(CH7_EN|CH6_DIS|CH5_EN|CH4_DIS|CH3_EN|CH2_DIS|CH1_EN|CH0_DIS);  // Enables only all odd channels

// Wr_Chn_Reg(CH7_EN|CH6_EN|CH5_EN|CH4_EN|CH3_EN|CH2_EN|CH1_EN|CH0_EN);   // Enables all Channels

  Wr_Chn_Reg(CH_ALL_DIS|CH1_EN|CH0_EN);

//  Config_Lmt_All(0x001,0x3cc);     // Configure All Low and Hi Limits

 //   Config_Hys_All(0x3bb);   // Configure All Channel Hysteresis

 

  //RBChn=Rd_Chn_Reg();  // Read Channel Register

//RBCon=Rd_Config_AD7091R();      // Read Configuration Register

//Rd_Chn_Def(0x0000);  // Defines the specified Channel's Limits and Hysteresis

// Rd_Chn_Def(0x0001);

}

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