I'm using the ADSP-21469 to communicate with two AD1974 chips using TDM. Since each of those chips carries 4 ADCs, we are using 8 channels. The SPORT configuration part of my code is as follows. It's roughly based on the Talkthrough example of the EZKit and it works perfectly:
// Clear out SPORT 1 registers.
*pSPMCTL1 = 0;
*pSPCTL1 = 0;
// External clock and frame syncs generated by AD1974.
// Receiver (SPORT1) at 12.288 MHz SCLK and 48 kHz sample rate.
*pDIV1 = 0x00000000;
// SPORT1 is being operated in "multichannel" mode - MCM.
// This is synonymous with TDM mode which is the operating mode for the AD1974.
// SPORT 1 Miscellaneous Control Bits Register
// SP1MCTL = 0x000000E2, Hold off on MCM enable, and number of TDM slots to 8 active channels.
// Multichannel Frame Delay=1, Number of Channels = 8, LB disabled.
*pSPMCTL1 = NCH7 | MFD1;
// Configures Chain Pointer Register for SPORT1A.
// Must point to last TCB of the sequence.
// Since it uses the chain pointer from TCB_B it.
// points to TCB_A with PCI bit.
*pCPSP1A = rxSport1.inputBufferTCB_B.chainPointer;
// SPORT1 control register set up as a receiver in MCM.
// SPORT1 control register SPCTL1 = 0x000C01F0.
// externally generated SCLK1 and RFS1.
*pSPCTL1 = SCHEN_A | SDEN_A | SLEN32;
// SPORT1 receive multichannel word enable registers.
// SPORT1 receive channels 0-7.
*pMR1CS0 = 0x000000FF;
// SPORT1 receive multichannel companding enable registers.
// No companding for the 8 active timeslots.
// No companding on SPORT1 receive.
*pMR1CCS0 = 0x00000000;
We are planning to use another audio source with this one, coming from an FPGA implementing an SDR (Software Defined Radio). This FPGA will implement the same TDM interface of the AD1974. We don't plan to mix the TDM stream of the ADCs with the TDM stream of the FPGA.
My question is: how should we configure the SPORT3 (I assume I have to use another SPORT, since 1 is busy with the ADCs) to operate with this new TDM stream? To simplify the understanding on how things will be provided by the FPGA, let's assume the new stream is like an AD1974 chip with 24 channels, transmitted at the same bit rate of the ADC chip. Clocks will be a responsability of the FPGA part.
My doubt is mainly on how to activate the channels on SPORT3 and whether they depend on the channels set for SPORT1.