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AD9528 PLL2 lock problem

Question asked by zeahr on Apr 20, 2017
Latest reply on Apr 27, 2017 by SteveO



I am using AD-FMCADC4-EBZ evalution board with 80MHz VXCO and I want to have a 614.4 MHz output.

Below are the following settings but unable to lock the PLL2.

VXCO = 80MHz
0x0207  R1 =  25  (0x19)
0x0204  M1  =   3  (0x03)
0x0208  N2 = 192 (0xBF)
0x0202  Doubler = 0x23 (enabled)
0x0203  Double/R1 Path = 0x10 (enabled)
0x0318  Ch8 Output Signal Source = 0x00 (PLL2/divider output)
0x031A  Ch8 Output Signal Divide ratio = 2 (0x01)
0x0201  VCO CAL Divider = 16 (0x10),  A=0, B=16. (stp output file value from AD9528 Evaluation Software)

The above settings met the Internal VCO requirements (3686.4 MHz) and should output 614.4 MHz at Ch8 port.
I did perform VCO calibration but the PLL2 won't lock, I suspect that the cause is the Feedback VCO CAL divider.
In the datasheet it is stated that the total Feedback VCO CAL divider (N = (P * B) + A) must be equal to M1*N2, but the limit of N is only 255.  (M1*N2 = 3 * 192 = 576 )

I tried different output (e.g. 153.6 MHz) with its corresponding PLL2 settings and N = M1*N2, the PLL2 was able to lock.
Is it possible to output 614.4 MHz with 80MHz VCXO without performing Calibration?


Thank you.