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ADF4150HV High speed PLL locking operation with Lower PLL phase noise.

Question asked by SKBY on Apr 20, 2017
Latest reply on May 22, 2017 by Brigid.Duggan

Dear Experts,

 

My customer is considering to apply ADF4150HV to the high speed PLL locking operation system with lower PLL phase noise. Could you please review below and then reply to the following questions?

 

I made the attached document. Could you please review the attached document at first? The attached document has included all of the following information with some customer's questions and some figures. The attached document must be helpful for you to easily understand the questions of my customer.

 

1. Customer's consideration to speed up the PLL locking time with lower PLL phase noise:
- My customer wants to achieve the PLL locking time at less than 50[usecs] with lower PLL phase noise than -126[dBc/Hz] at 62.5[kHz] offset.

 

- My customer is considering to put two sets of "ADF4150HV and Loop Filter" as illustrated on the p.5 of the attached document.

 

- My customer is considering the following scenario with the following operation-order in order to achieve the high speed PLL locking operation with both of shorter PLL locking time than 50[usecs] and lower PLL phase noise than -126[dBc/Hz] at 62.5[kHz] offset. Please refer to the pp.4-8 of the attached document at first.

 

a) Fast locking mode operation (Refer to the p.6 of the attached document):
The ADF4150HV#0 is trying to lock the VCXO output clock to the reference clock with wide bandwidth loop filter as illustrated on the p.6 of the attached document.

 

b) Operation transition mode (Refer to the p.7 of the attached document):
Once the ADF4150HV#0 with the wide bandwidth Loop Filter#0 locks the VCXO output clock to the reference clock, the Loop Filter#0 conditions such as the loop filter output voltage and so on will be copied to the Loop Filter#1 with narrow bandwidth as illustrated on the p.7 of the attached document.

 

c) Normal tracking mode operation (Refer to the p.8 of the attached document):
The ADF4150HV#1 takes over from the ADF4150HV#0 and then keeps on locking the VCXO output clock to the reference clock with the narrow bandwidth Loop Filter#1 in order to achieve lower PLL phase noise than -126[dBc/Hz] at 62.5[kHz] offset as illustrated on the p.8 of the attached document..


2. Questions of my customer:
Could you please reply to the following questions with the attached document?

 

Q1: How do you think about the fast PLL locking scheme with lower PLL phase noise as described in the attached document? Is this implementation reasonable? Do you know any risk/disadvantage over this implementation?

 

Q2: If you know how to achieve the PLL locking time at less than 50[usecs] with lower PLL phase noise than -126[dBc/Hz] at 62.5[kHz] offset, please advise us about how to implement it for the requirements.

 

Q3: After it was moved to the normal tracking mode operation as illustrated on the p.8 of the attached document, the ADF4150HV#0 indicated "Unlocked state" through "LD#0". We supposed that the ADF4150HV#0 would keep on indicating of the locked state after it was moved from the fast locking mode operation to the normal tracking mode operation. Is it reasonable that the ADF4150HV#0 indicates the "Unlocked state" through "LD#0" signal in the normal tracking mode?


Thanks and regards.

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