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AD9680 RF signal spectrum design consideration.

Question asked by SKBY on Apr 19, 2017
Latest reply on May 1, 2017 by SKBY

Dear Experts,

 

My customer is considering to apply AD9680 to an RF system. Could you please review below and then reply to the following questions and concerns?

 

I made the attached document. Could you please review the attached document at first?


1. AD9680 Usage specifications of my customer: (Note: Please refer to the p.3 of the attached document also.)
1) # of ADC input channels: 2 channels.
2) ADC sampling rate (fs): 1228.8[Msps].
3) # of Quantization bits: 14 bits.
4) I/Q mixing: Yes.
5) I/Q mixing frequency: 307.2[MHz] (:=fs/4).
6) HB1 Decimation ratio: 2.
7) # of the virtual converters: 4 channels.
8) # of JESD204B-I/F lanes: 4 lanes.


2. Questions of my customer:
Could you please reply to the following questions?

 

Q1: The original frequency bandwidth of the ADC input signal is less than 614.4[MHz] for 1228.8[Msps]. After the I/Q mixing with the I/Q mixing frequency at 307.2[MHz] in AD9680, the frequency bandwidth is changed to the half one at less than fs/4=307.2[MHz] as illustrated on the p.6 of the attached document. Is it correct?

 

 

Q2: If the reply to the above question, "Q1" is "Yes", the decimation ratio in the HB1 of AD9680 will be able to be set to 2 as illustrated on the o.4 of the attached document. Therefore, my customer believes that we can calculate the following JESD204B-I/F Lane Line Rate.


Could you please review the following calculation of the JESD204B-I/F Lane Line Rate and advise my customer about any error, if you find?


(Lane Line Rate) = (# of ADC input channels) x (I/Q mixing channels) x (16 bits) x (10/8) x (ADC sampling rate ) / (HB1 Decimation ratio) / (# of JESD204B-I/F lanes).
= (2 channels) x (2 channels) x (16 bits) x (10/8) x (1228.8[Msps] / 2) / (4 lanes)
= 12288[Mbps] = 12.288[Gbps].


Moreover, could you please review the p.5 of the attached document?


Is the above calculation correct?

 

 

Q3: When my customer applies the block diagram as illustrated on the p.4 of the attached document, my customer will use "Two DDC mode" as described on "Table 25" of the p.70 of the AD9680 Datasheet Rev.C.

Is it correct?

 

 

Q4: AD9680 can support 2-channel ADC analog inputs and 4-channel (:=2chxI/Q 2ch) ADC outputs with 12288[Mbps] x 4 JESD204B-lanes in the application as described/illustrated on the p.3 and p.4 of the attached document. Is it correct?


Q5: When the ADC sampling rate is 1228.8[Msps] with HB1 Decimation ratio at 2, the "Alias Protected Bandwidth" will be 473.088[MHz]. Is it correct?

 

 

473.088[MHz] = (481.25{MHz]/1250[Msps]) x 1228.8[Msps]. Moreover, please refer to the "Alias Protec ted Bandwidth" description on the p.3 of the attached document.

Q6:
If you find any concern, issue, error and/or problem in the attached document and the questions, could you please advise my customer about it?


Thanks and regards.

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