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Issues we are having with the ADV7125

Question asked by APZ Employee on Apr 19, 2017
Latest reply on Apr 25, 2017 by tjohn28

The original design was developed with the AD9701 DAC ECL input design with -5.2 V supply, the re-spin utilizes the ADV7125 DAC TTL input design with +5 V supply as the replacement. The issue we have encountered is the Video Waveform output for the original design the Blanking level is 0.0V and for the new design the Blanking level is 0.4V. In the original design ADI recommend to incorporate an op-amp circuit to invert the signal to compensate for the 0.4 V offset. Unfortunately the design has created undesirable effects on the output signals labelled DAC GAIN and PIXEL OFFSET CORRECTION and they don’t meet the current signal specifications. Also the original designer is no longer with us so we are at a disadvantage there. This is a major concern we built five assemblies with the thought of going into production once we fully evaluated the system, but if we need to re-spin the design again this will be an even greater concern.