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ADV7511 on KC705 How to modify the reference design to use embedded syncs?

Question asked by MaciejSD on Apr 19, 2017
Latest reply on Apr 21, 2017 by MaciejSD

Hello,

 

In my new project I use the ADV7511 HDMI transmitter with embedded syncs. For prototyping I'm using the KC705 board in which I successfully ran the reference design as it was. Now I'm trying to make it use the embedded syncs instead of separate syncs. I changed the "axi_hdmi_core" (axi_hdmi_tx.v) verilog parameter EMBEDDED_SYNC to 1 and the no-OS software transmitter.c file TransmitterParm.InPixelFormat to SDR_422_EMP_SYNC or SDR_422_EMB_SYNC_2X_CLK or DDR_422_EMB_SYNC, but it just doesn't work at all (the display is blank). The UART output console is as below.

 

Please kindly advise what needs to be done to make it work. My target is 1080p60, YCbCr 4:2:2 at 8 bits per color, and embedded syncs.

 

Best regards,
Maciej

 


********************************************************************
  ADI HDMI Trasmitter Application Ver R1.1.1
  HDMI-TX:  ADV7511 Rev 0x14
  Created:  Apr 19 2017 At 18:46:12
********************************************************************

 

Mute audio and video.
APP: Driver Enabled
HPD changed to HI
MSEN changed to HI
APP: Changed system mode to Transmitter
A new EDID segment was read.
DVI device.
------------------------- EDID BLOCK 0 -------------------------
Checksum failed on block 0.
Un-mute audio and video.
HPD changed to HI
MSEN changed to HI
A new EDID segment was read.
HDMI device.
------------------------- EDID BLOCK 0 -------------------------
Edid Version 1.3
Mon Timing:
    Pixel clock = 148.50 MHz
    H Active    = 1920
    V Active    = 1080
    Progressive
    No stereo
    Separate sync = 3
    -ve Vsync
    +ve HSync
Mon Timing:
    Pixel clock = 146.25 MHz
    H Active    = 1680
    V Active    = 1050
    Progressive
    No stereo
    Separate sync = 3
    +ve VSync
    -ve HSync
Mon Freq:
    Min V Freq = 56 Hz
    Max V Freq = 75 Hz
    Min H Freq = 30 KHz
    Max H Freq = 83 KHz
Mon Name:   2D FHD LG TV
Edid extensions blocks: 1

 

========================= EDID BLOCK 1 =========================
CEA extension block revision 3
Underscan=Yes  Audio=Yes  YCbCr4:4:4=Yes  YCbCr4:2:2=Yes
Data block collection information:
    Video data block
       * VIC=4
         VIC=5
         VIC=3
         VIC=2
         VIC=32
         VIC=34
         VIC=16
         VIC=17
         VIC=19
         VIC=18
         VIC=20
         VIC=31
         VIC=7
         VIC=22
    Audio data block
       Format Code          = 2 (AC-3)
        Max. No. of Channels= 6
        Sampling Freq. (KHz)= 32  44.1  48  
        Max. Bit Rate       = 640 KHz
       Format Code          = 1 (Linear PCM)
        Max. No. of Channels= 2
        Sampling Freq. (KHz)= 32  44.1  48  
        Length (bits)       = 16  20  24
    VSDB data block
SPA location is at 0x9E, SPA = 1.0.0.0
Mon Timing:
    Pixel clock = 74.25 MHz
    H Active    = 1280
    V Active    = 720
    Progressive
    No stereo
    Separate sync = 3
    +ve VSync
    +ve HSync
Mon Timing:
    Pixel clock = 74.25 MHz
    H Active    = 1920
    V Active    = 540
    Interlaced
    No stereo
    Separate sync = 3
    +ve VSync
    +ve HSync
Mon Timing:
    Pixel clock = 74.25 MHz
    H Active    = 1920
    V Active    = 540
    Interlaced
    No stereo
    Separate sync = 3
    +ve VSync
    +ve HSync
Mon Timing:
    Pixel clock = 148.50 MHz
    H Active    = 1920
    V Active    = 1080
    Progressive
    No stereo
    Separate sync = 3
    +ve VSync
    +ve HSync
Mon Timing:
    Pixel clock = 148.50 MHz
    H Active    = 1920
    V Active    = 1080
    Progressive
    No stereo
    Separate sync = 3
    +ve VSync
    +ve HSync
########################### EDID END ###########################

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