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configuration for packed i2s mode on 21371

Question asked by esfld on Sep 29, 2011
Latest reply on Oct 5, 2011 by esfld

Hello,

 

I have two 21371 processors on a custom board.  They are each currently receiving/transmitting 4 distinct i2s serial streams from/to codecs.  I have DMA enabled on these channels so that I get an interrupt whenever I get both channels in the i2s signal for all four streams.  They all share the same frame sync and clock signal (externally generated).

 

What I would like to do now is enable these two sharcs to send their serial data output (from each of their transmitted i2s channels) to each other as an "i8s" data stream, at a data rate 4 times greater than the i2s rate, so that every frame sync period, a sharc gets 8 channels from the other sharc, in addition to the 8 channels (4 * i2s) from the ADCs.

 

The only connections I have between the two SHARCs are the "i8s" in/out data streams; I have no dedicated clock signal for i8s data.  Can I generate this clock signal internally on both sharcs, based on the FS or data clock input?  So if each SHARC is using an internal bit clock that is a multiple of a common signal coming from the DACs, they should stay in sync?  And can I still use the same frame sync input from the codecs for the i8s lines?  Will this work, or do I need additional connection(s)?

 

The attached document shows the setup; the other sharc looks exactly the same except the S8_DO_X and S8_DI_X lines are reversed.

 

Thanks,

Ethan

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