I enabled all 4 channels in AD7175-2, and set the ODR to 17,857SPS.
Using single conversion mode to sample all the channels by writing to ADC Mode register with 0x4010.
The settling time of first channel ( time after writing the ADC Mode register to the first falling edge of RDY) is about 78us.
Settling time of the later 3 channels( time between adjacent falling edge of RDY) is 56us, which is the same as the datasheet discribed.
So why the first settling time takes 20us more？