Is this possible to use in AD991x (e.g. AD9915) SYNC_CLK slower than 156MHz?
It based on need to use instead PLD (reconfig and management) fast microcontroller.
Maybe you can also share info (AN, reference design, …) with similar solution?
The SYNC_CLK is directly related to the reference/sample clock. If you want that signal to go slower, just run the sample clock slower, keeping in mind the Nyquist implications. Referencing the AD9915 specifically, they SYNC_CLK runs at 1/16th the speed of the sample clock.
If you prefer to keep the sample rate higher, the AD9914 SYNC_CLK runs at 1/24th the sample rate. The AD9914 offers the largest gap between sample rate and the SYNC_CLK.
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