I use zynq and AD9361's TX1 send data , RX1 receive data , baseband data source is the default HDL project DDS , frequency is 480KHz; set internal RX LO frequency 2.3GHz , as same as Tx LO. The data rate of TX path and RX path is all 30.72MHz, so the number of sampling points in a baseband signal period is 30.72e6/480e3=64 .
But when i plot the receive data I and data Q with interval 48 baseband signal periods(3072 sampling points), i find the signal's phase has slowly offset:
when i plot the receive data I and data Q with interval 3075 sampling points, there is no phase offset.
I guess the cause of this issue is because the ADC clock and DDS clock phase offset, but when I set the DDS frequency to 0, TX LO - RX LO = 480kHz, the issue still exists, and someone can help me analyze