In the process of evaluating the AD9912 on the AD-provided eval board, I notice a situation in which the output frequency does not match what the eval software claims it should be.
This seems to happen when using the internal SYSCLK PLL mulitplier part of the circuit.
For instance, I'm using a 25MHz input to SYSCLK with the default 40x mulitplier to get a 1GHz DAC clock.
I ask the DDS to produce a 21MHz CMOS output, but instead I get 28MHz.
However if I bypass the PLL multiplier completely and input 1GHz (or 900MHz) to SYSCLK directly, I get the correct 21MHz output.
I attached a snapshot of the settings I used, plus a snapshot of the output producing the wrong frequency (28MHz).
Am I missing something here, or do I have a malfunctioning device?
I checked the eval board for any missing components or incorrect configurations, but everything seems to be in the right places.
Any advice is much appreciated!