I don't see it implicitly stated any where but is it important that the LVDS interface trace lengths are the same length from the FPGA to both AD9361s?
I know in the HDL the l_clk is tied from core 0 to the clk input of core 0 and 1.
I am aware that the data sheet says that the 40 MHz buffered clk trace lengths should be the same.
If the traces cannot be made the same, how can I account for this on the HDL - No-OS side? I would be okay with loosing the ability for chip to chip synchronization as long as I can still get synced 1RX2RX from each chip.