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AD9642 - how does the clock divide/delay work

Question asked by pontus on Apr 18, 2017
Latest reply on Apr 26, 2017 by pontus

I have tried to divide by 2 (works fine) then to using delay=0 or delay=1 (both accessed in reg 0x0B) but I see

no delay on the sampled signal (I have a synchronous pulse test wave form).

The datasheet page1-figure1 , or page6-figure2 gives no hints on how the delay is generated/applied.


-- PS