Firstly please look into the attached diagram.
In this system, AD9528 requires to distribute devclock/SYSREF to 8 devices (four ADCs and four JESD204B RX IP cores in FPGA). Because 16 outputs are required thus it exceeds 14 outputs of AD9528, two clock buffers are placed for four JESD204B RX IP cores in FPGA. Using the clock buffers have some concern. Additional jitter by the clock buffers, skew among outputs of clock buffers (setup and hold time at SYSREF and strict timing alignment among sysref).
If there is other better way of devclock/SYSREF distribution, could you please present it?