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lvds interface

Question asked by manideep on Apr 15, 2017
Latest reply on Apr 19, 2017 by sripad

Hi to all,

 we are using our own HDL routines to generate the data and we are analyzing the data using chip scope analyzer. I have configured the device  DUAL PORT full duplex and LVDS mode and I am following the timing diagram as shown in the figure 80 of UG673  for  ad9364. The generated  data( i.e filtered data I and Q) transmit to the AD9364 from the FPGA  as per the 

timing diagram mentioned in the above.

              To test the data interface we did the loop back test  by setting 0x01 in register 0x3F5 and below are the delay settings:

    0,        //single_data_rate_enable *** adi,single-data-rate-enable
    1,        //  1 lvds_mode_enable *** adi,lvds-mode-enable
    0,        //half_duplex_mode_enable *** adi,half-duplex-mode-enable
    0,        //  DUAL , single_port_mode_enable *** adi,single-port-mode-enable
    0,        //full_port_enable *** adi,full-port-enable
    0,        //full_duplex_swap_bits_enable *** adi,full-duplex-swap-bits-enable
    0,        //delay_rx_data *** adi,delay-rx-data
    4,        //rx_data_clock_delay *** adi,rx-data-clock-delay
    7,        //rx_data_delay *** adi,rx-data-delay
    4,        //tx_fb_clock_delay *** adi,tx-fb-clock-delay
    7,        //tx_data_delay *** adi,tx-data-delay
    150,    //lvds_bias_mV *** adi,lvds-bias-mV
    1,        //lvds_rx_onchip_termination_enable *** adi,lvds-rx-onchip-termination-enable

              By analyzing the RX data is not  resembles the tx data which is sent to the AD9364.please find the attachments of tx and RX data .

 

please make sure where the problem exists for this behavior?

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