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What are the logic levels for the GPIO pins when they are beings used as JTAG?

Question asked by rhickling@innovative-dsp.com on Apr 14, 2017
Latest reply on Apr 17, 2017 by sripad

I'm wondering if the logic levels GPIO_4, 5, 6, and 18 are still governed by VDDA_IF when those ports are used as JTAG pins?

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