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When does l_clk become stable?

Question asked by D-Tech on Apr 14, 2017
Latest reply on Apr 18, 2017 by rejeesh

HDL: FMCOMMS 5 hdl-hdl_2015_r1

 

I am clocking data out of the util_adc_pack_0 into 4 FIFOs that runs at l_clk. This clock is all over the place when the system starts up and I believe it is causing issues. I end up with some FIFOs getting more or less data which throws any phase comparisons I do from channel to channel off.

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