AnsweredAssumed Answered

AD9648 goes in deadlock state at initialization

Question asked by Nel_ge on Apr 13, 2017
Latest reply on Apr 18, 2017 by Nel_ge

Hello,

 

In our current design, after multiple power ON/OFF, we face the issue that sometimes (~5%) we get the following situation:

 

  • AD9648 does not provide a valid output clock. (But input clock (based on DDS) is always OK)
  • AD9648 is no more resettable with digital reset.

 

In few words, AD9648 is in an undetermined state and can not recover.

 

This kind of problem were already reported here :

 

 

We modified our initialization sequence in several ways :

Trial 1 : Power up (All supplies start together) ->Clock input initialization (DDS based) -> ADC initialization (with digital reset)

Trial 2 : Power up (All supplies start together) ->ADC in full power-down mode -> Clock input initialization (DDS based) -> ADC initialization (with digital reset)

Trial 3 : Power up (All supplies start together) ->Clock input initialization (DDS based) -> No reset on ADC

 

No sequence improves our failure rate.

We are not able to prevent AD9648 to go in this undetermined state.

 

To better describe our hardware configuration : SYNC = PDWN = OEB = GND , VREF = VCM = GND, Clock input is differential

 

We need help or new ideas…

 

Thank you, Best regards,

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