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Line length of Device clock and SYSREF in multi device use case

Question asked by katsu on Apr 8, 2017
Latest reply on Apr 9, 2017 by katsu

Hello,

 

Two ADCs (AD9680), one clock generator (AD9528) and one FPGA is a target system. A Clock generator distributs Device clock and SYSREF to two ADCs and a FPGA.
Assuming that
Line length of Device clock and SYSREF between ADC1 and Clock generator = L1,
Line length of Device clock and SYSREF between ADC2 and Clock generator = L2,
Line length of Device clock and SYSREF between FPGA and Clock generator = L3.
Does Line length need to be L1=L2=L3?
Or L1≠ L2≠ L3 is acceptable?

 

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