A customer is experiencing the following issue:
"I had one additional question regarding the building of ADI provided HDL for the AD9371. I am able to git clone and build the required HDL without any trouble. That is, the makefile and tcl-based approach works just fine with the appropriate version of Vivado (here I am referring to building the AD9371 branch within hdl_2016_r2 repository using Vivado 2016.2). I can then open the generated project in the GUI, where I can interact with the block diagram. However, if I run synthesis and implementation again (WITHOUT changing anything), the design no longer passes timing. It appears that some of the constraints “get lost”, but I am uncertain which constraints are disappearing."
There appears to be at least one other instance of this occurring (https://ez.analog.com/thread/72113). Lars refers to needing “the fix” when constraints go missing for FMCOMMS2 (FMC board for the AD9361). Upon further investigation of “the fix” it appears that it has already been applied to hdl_2016_r2, but I am observing timing closure issues just the same. Can you advise on which constraints might be disappearing when interacting with the GUI? Most of my timing issues seem to be related to the HDMI functionality."