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AD-FMCOMMS2-EBZ / Xilinx LVDS timing calibration

Question asked by RobB Employee on Apr 7, 2017
Latest reply on Apr 11, 2017 by larsc

Hi,

 

One of our customers is working with the AD-FMCOMMS2-EBZ and a Xilinx ZED board for the processing. Could you please help out with the following:

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We see that inside the AD9361 interface for Xilinx, there is a delay line in the receive path for the LVDS
data inputs from the AD9361 ADC's. This delay needs calibration to compensate for the circuit delay of
the LVDS clock input buffer inside the Xilinx fpga. To calibrate this delay line, a function need to be run,
and it would be nice if you could point us to the correction function to run.
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Thanks!

Best regards,

Rob

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