Hello, ADI Support Team
I could find the description of Power Up Sequence in ADAU1452 Datasheet as follow.
All power pins can be supplied simultaneously.
<Page 25 & Page 26>
If possible, apply the required voltage to all four power supply domains (IOVDD, AVDD, PVDD, and DVDD) simultaneously
Therefore, I could understand all power can be supplied at the same timing.
However, I am concerned about the following description.
When a crystal is in use, the crystal oscillator circuit must provide a stable master clock to the XTALIN/MCLK pin by the time the PVDD supply reaches its nominal level.
Does this mean that PVDD should supply after XTALIN stable?
In other word, does this mean that IOVDD and PVDD can not be supplied at the same timing, when a crystal is in use?
If so, I think the explanation contradicts.
Best Regards, TomY