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HDL reference design project adrv9371x/zc706 compilation failed on Vivado 2016.2

Question asked by scout on Apr 6, 2017
Latest reply on Apr 12, 2017 by rejeesh

I downloaded the branch at GitHub - analogdevicesinc/hdl at hdl_2016_r2 , installed vivado 2016.2,  and go into the ADRV9371X/ZC706 project and "make -C projects/adrv9371x/zc706", and vivado reported this error:

ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
i_system_wrapper/system_i/axi_ad9371_tx_jesd/inst/i_system_axi_ad9371_tx_jesd_0 (jesd204_v7_0_1_top__parameterized1)
i_system_wrapper/system_i/axi_ad9371_rx_os_jesd/inst/i_system_axi_ad9371_rx_os_jesd_0 (jesd204_v7_0_1_top__parameterized0)
i_system_wrapper/system_i/axi_ad9371_rx_jesd/inst/i_system_axi_ad9371_rx_jesd_0 (jesd204_v7_0_1_top)

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