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booting Sharc 21489 - ldr file boot stream doubt

Question asked by BlackBeauty on Apr 5, 2017
Latest reply on May 8, 2017 by Jithul_Janardhanan

Hi everyone, 

I have been trying to boot the ezkit21489 board in slave spi mode from a host microprocessor with no success. And I am trying to understand the ldr stream file in order to transmit it correctly to the dsp.

So far:

-I have a spi master running slowly to avoid the zero loading overhead (about 50KHz) (uC)

-I have "lifted" the output of the reset IC in the EZKIT board just in case it was interfering with my RST signal.

-Board configuration for booting is ok. Board switches are configured to allow external signals as spi, rst and so on.

- I generate the ldr file in spi slave mode hex mode. 

- I have tried : to boot only the well known kernel 489_spi provided in the forum which toggles a flag at zero loading. Also the same with the infinite loop in the init user to toggle a led and check it is properly loaded but no success so far.

 

My doubt is regarding the byte stream. I have read that it has to be in a 6bytes manner (due to the 48bits kernel instructions) depending if it spi is 8/16/32 bits as indicated in the HW reference manual. But i have realised that :

 

the ldr kernel file at CCES indicates and starts as

 

BLOCK 0 at 0x0. ZERO L48 0x2 Address 8c000 Payload N/A ByteCOunt 0x0005

Target address      Prom Address    Block Payload

                                                          No Payload

 

BLOCK 1 at 0xC INIT L48 0x5 Address 8c005 Payload 48 byte ByteCOunt 0x0420

Target address      Prom Address    Block Payload

0x0008C005             0x0000001C   06BE0408C09D 0F7B00000000 0F7A00000000

...

...

 

BLOCK 2 at 0x438 FINAL INIT 0x0 Address 0 Payload N/A byte ByteCOunt 0x0000

Target address      Prom Address    Block Payload

                                                          No Payload

 

And the ldr file in a text editor starts like this:

 

0x02,0x00,0x00,0x00,0x05,0x00,0x00,0x00,0x00,0xc0,0x08,0x00,

0x05,0x00,0x00,0x00,0xb0,0x00,0x00,0x00,0x05,0xc0,0x08,0x00,

0x9d,0xc0,0x08,0x04,0xbe,0x06,0x00,0x00,0x00,0x00,0x7b,0x0f,

0x00,0x00,0x00,0x00,0x7a,0x0f,0x00,0x10,0x00,0x00,0x02,0x14,

0x00,0x00,0x00,0x00,...

 

They (CCESS ldr and text file and then my .c file) are in a reverse byte order. And which is the meaning of the first 2 lines??first line is realted the BLOCK 0 at 8c000, and second related BLOCK 1 at 8c005

 

How I should build the boot stream from host to dsp processor in 8 bit mode?

I have tried so far sending the ldr shown in the text editor (asit were stored in an unsigned char hex[]; )

hex[5]-hex[4]-hex[3]-hex[2]-hex[1]-hex[0]-hex[11]-hex[10]-hex[9]-hex[8]-hex[7]-hex[6]-hex[12]..... upto the end of the kernel size -

 

if the generated kernel length is shorter than the kernel defined size 1536 bytes. Should I send bytes 0x00 upto the 1536 byte count.

After that i wait a "moderated" amount of time and the I send my app code (if I tried to boot a kernel with no infinite loop at the end and I have tried both the same 6bytes inverse order and also byte to byte from 0 to the end).

 

HW reference tells about sending the kernel in the 48 bit fashion transmiting, but, is it that only related to kernel??how should I arrange the byte stream for the app ldr??

 

I would appreciate some light on it ;D

 

BR and thanks in advance

CM

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