I am trying to learn more about the AXI AD9361 IP core. After looking at the wiki page ( AXI_AD9361 [Analog Devices Wiki] ), I have two questions related to the ADC and DAC data channels.
1) Under what conditions is the "enable" signal that is associated with each data channel asserted/deasserted? The wiki seems to imply this directly reflects software-side channel enable settings, is this correct? Are there any data flow or other reasons the enable line would change state?
2) Each channel has its own "valid" signal, and I and Q data lines are routed as separate channels. It seems you'd want I and Q data aligned and then have a single "valid" flag for them. Are there ever any conditions where the I and Q data channel "valid" signals would have different states? Are the I and Q samples always guaranteed to be aligned in time? Is there any suggested way to handle the I and Q valid signals in custom processing (eg, if you get a condition where I is "valid" and Q is not "valid"?)
I appreciate any clarification on this!