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FMCOMMS5 Problems

Question asked by D-Tech on Apr 5, 2017
Latest reply on Apr 18, 2017 by D-Tech

Using:
hdl_2015_r1
no-OS-2015_R1

 

Vivado Project changes:
Added custom IP that ties into util_adc_pack_0 dvalid and ddata[127:0]

 

No-Os changes:
0,  //frequency_division_duplex_mode_enable
56000000,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz
56000000,//rf_tx_bandwidth_hz *** adi,rf-tx-bandwidth-hz
1,  //digital_interface_tune_skip_mode *** adi,digital-interface-tune-skip-mode
1,  //half_duplex_mode_enable *** adi,half-duplex-mode-enable ---------------------------------
1,  //rx1rx2_phase_inversion_en *** adi,rx1-rx2-phase-inversion-enable-------------------


I manually set the sampling freq to 61440000 for ad9361_phy and ad9361_phy_b then go to TDD RX mode by moving through the ENSM states to Alert then RX for both phy and phy_b.


I see on the terminal:

 ad9361_init: AD9361 Rev 2 succ. init
 ad9361_init: AD9361 Rev 2 succ. init
 I print out the ENSM states as I move to RX. 
 + all the console commands

 

No init/cal failures up to this point.
 
Problems:

1) The console comands just return 0. Does this feature only work for single AD9361 chip dev boards?

2) I am running a 2.415 GHz signal into the RX1A and RX2A rf ports of both chips. I can see the 15 MHz mixed product output on the ILA attached to the ddata port of util_adc_pack_0 for what looks like RX1 and RX2 for the first AD9361 but I see just noise on the RX xhannels for the other chip. Seems like AD9361 number 2 is not initializing correctly.

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