I have an FMCOMMS2 board with ADI9361 RFIC and am able to send our waveform files from the Zed board, then demodulate it with an external Signal analyzer. The problem is, our waveforms support very slow symbol rates and I cannot set the baseband interface clock slow enough to achieve the desired symbol rate. Slowest clock rate the GUI allows is 1.05MHz. Also the Tx DAC and Rx ADCs are set to the same rate. How do I control the clock divider for the Tx DAC?
I assume I can use the interpolation filters in the Tx path to achieve a slower Tx symbol rate. How do I control these?
We cannot do our Tx performance measurements until I can configure the platform to transmit at 23.4K symbols/sec and right now the slowest rate I can get is around 500K symbols/sec.