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AD9129 Controller Clock Divider bits are defined in the Data CTRL 1 register 0x0B of the 9129.  We have always set this register to DCI/512 because the example set up in the data sheet says to.  What does this register setting do in the part? Are there ad

Question asked by Bill.AvidSystems on Apr 4, 2017
Latest reply on Apr 4, 2017 by danf

The AD9129 Controller Clock Divider bits are defined on Data CTRL1 register 0x0B.  We have always set this register to be DCI/512 because of the example set up in the data sheet but we don't really know what it does.  I suspect it sets a divider for the DCI clock that is then used to operate the DLL but the data sheet does not actually say that.  Are there any advantages to setting this register differently?  Why does it need to be set at DCI/512?

Thanks

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