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DDR2 get access to bank1?

Question asked by mich1985 on Apr 4, 2017
Latest reply on Jan 9, 2018 by Jithul_Janardhanan

Hello all,
currently I'm trying to test the DDR2 RAM (MT47H32M16NF-25E IT) on one of our custom boards with the DMA based power on self test example (which is part of the ADSP 21469 EZKit examples). The test runs fine for the first 248 MB (bank 0). If I'm trying to use memory locations above 248 MB the test fails.

 

Test result for 248 MB:

 

Testing 260046848 bytes,
address range: 0x200000 - 0x3ffffff


Test result for 252 MB:

 

Testing 264241152 bytes,
address range: 0x200000 - 0x40fffff

 

Failure at address 0x4000000: expected 0x0, received 0x1fd01fc

 

My current DDR2 related configuration is as follows:

 

<DDR2 Cfg>
*pEPCTL = B0SD | B1SD | EPBRROT | DMAPRROT | NOFRZDMA | NOFRZCR | NOFRZSP;

 

*pDDR2RRC =    (0x1D << 21) | (0x6CD);    /* timing stuff */

 

*pDDR2CTL1 =DDR2TFAW12 | DDR2TRRD3 | DDR2TRTP2 | DDR2TRCD4 | DDR2TWTR2 | DDR2TRP4 | DDR2TRAS10;

 

*pDDR2CTL2 =DDR2MR | DDR2TWR4 | DDR2CAS4 | DDR2BL4;

 

*pDDR2CTL3 =DDR2EXTMR1 | DDR2AL0 | DDR2ODTDIS;

 

*pDDR2CTL4 =DDR2EXTMR2;

 

*pDDR2CTL5 =DDR2EXTMR3;

 

*pDDR2CTL0 =DDR2PSS | DDR2RAW13 | DDR2CAW10 | DDR2BC4 | DDR2WDTHx16 | DDR2OPT | DDR2MODIFY2;
</DDR2 Cfg>


So is it necessary to "manually activate / select" the memory bank before accessing it? 

 

Best regards,

 

flo

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