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Setup and hold timing in AD9670

Question asked by Stef_D on Apr 4, 2017
Latest reply on Apr 10, 2017 by Stef_D

Hi,

 

I am trying to interface the AD9760 with a FPGA, I need to constrain timing input.

 

In datasheet, it talks about DCO to Data (Tsample/28 +/- 300ps).. 

In worst case, I guessed that setup and hold time are Tdco/4 - 300ps. But it is not clear for us!

 

So I write the SDC : 

 

 create_clock -name {Virt_Clock1} -period 2.857 -waveform { 0.000 1.428 }   //350 MHz

 set_input_delay -min -clock Virt_Clock1 -0.3 [get_ports {DATA_MP_1*}]
 set_input_delay -max -clock Virt_Clock1 0.3 [get_ports {DATA_MP_1*}]
 set_input_delay -min -clock Virt_Clock1 -0.3 [get_ports {DATA_MP_1*}] -clock_fall -add_delay
 set_input_delay -max -clock Virt_Clock1 0.3 [get_ports {DATA_MP_1*}] -clock_fall -add_delay

 

Are Setup and hold time correct? and Constrain script too? 

 

Thank you

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