Can the AD9364 run in TDD mode at 64M samples/sec (128 MHz DDR clock) with the RF data buses in LVDS mode? (i.e. is that a valid configuration?)
Max data rate supported by AD9364 is 61.44 Msps(122.88 clk rate).
Yes it is a valid configuration.
So you are saying that the TDD mode and LVDS mode is a valid configuration, however running it at 64Msps is NOT? Please confirm.
It cannot be run at 64 Msps.
If it cannot be run at 64 Msps, then I have 2 follow-up questions:
1) In UG-673 (Rev 0), page 100, there is a chart indicating "Maximum Data Rate—Combined I and Q Words (MSPS)", and the populated value is 122.88. Perhaps this refers to I alone (or Q alone), which would make I and Q combined over the link 122.88 / 2 = 61.44. Or perhaps it's just a typo.
2) On the same page, the following text appears: "The maximum DATA_CLK rate is increased to 245.76 MHz in LVDS mode". Considering this value, I imagine the equivalent rate to handle I and Q words, high and low nibbles, would be 245.76M / 2 / 2 = 61.44M. However, with DDR, the rate should be 61.44M x 2 = 122.88M. Is there an error in my math?
Data rate from transceiver POV is combined IQ.
1. Yes it is a typo error
2. Yes data_clk can go upto 245.76 MHz and your calculation is correct but the maximum data rate at FIR output and input is 61.44 Msps. Even though interface and clk supports higher rate this limits the data rate.
Thanks for your response!
So if the max rate is 61.44 Msps, is there any reason or use-case where programming data_clk to 122.88 MHz or greater is valid? Also, does the 61.44 Msps limitation exist even if we bypass the FIR?
In DDR LVDS case the data_clk needs to be 122.88 MHz.
Yes even if you bypass FIR still the max data rate is 61.44 Msps.
In UG-673 (Rev 0), page 88, Table 51, there is a listing of the various rates for various configurations of CMOS mode. For "dual port half duplex", the table indicates that 122.88 Msps is achievable with DDR. Is this another typo?
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