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Timing constrains are not met in HDL that have been modified

Question asked by a820083502 on Apr 1, 2017
Latest reply on Apr 3, 2017 by a820083502

Hello Everyone, 

I am using AD-FMCOMMS4-EBZ(AD9364)board and Xilinx ZC706 board. HDL libraries and projects branch is hdl_2016_r1(master branch),Vivado version is 2015.4.2.

In order to add my own modulation module(pi/4 DQPSK),I delete util_ad9361_dac_upack which in your design and add my custom modulation IP 

When I write_bitstream ,in Implementation stage,Vivado prompt implementation failed,The report shows:

 

Full timing report in attachment.

 

What’s more,if I ignore it and go on to next step ,vivado can generate bit file successfully,I launch SDK and program FPGA and debug it using ILA,I can get correct baseband signal. It seems that the error has no effect on the project.But I still want to know what it mean and how to fix it.Thanks in advance!

 

Regards

Liu

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