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AD9361 LVDS timing

Question asked by komo Employee on Mar 31, 2017
Latest reply on Apr 19, 2017 by sripad

In looking through the AD9361 documentation (Datasheet and UG-570) I cannot seem to find much information on the LVDS data interface other than basic timing and voltage information.


In particular, I am looking for the following information:

  1. What is the on-chip LVDS receiver tolerance for intra-pair skew?
  2. What is the on-chip LVDS generator intra-pair matching (at the BGA ball) for launch time?
  3. What is the on-chip LVDS receiver eye mask requirement at maximum bus speed (492 Mbps)?
  4. Are there any maximum inter-pair skew requirements other than meeting appropriate setup/hold times specified in the datasheet?


We are currently in placement portion of layout, and need this information for allocating routing budgets across our three boards (Digital, Flex interconnect, and RF board).