AnsweredAssumed Answered

AD9361 calibration timeout

Question asked by ENGINEER on Mar 30, 2017
Latest reply on Apr 8, 2017 by rgetz
Branched from an earlier discussion

Hi Lars,

             I reached there with Petalinux

 

[ 3.611786] ad9361 spi32766.0: ad9361_probe : enter (ad9361)
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[ 4.388152] ad9361 spi32766.0: Calibration TIMEOUT (0x5E, 0x80)
[ 5.154967] ad9361 spi32766.0: Calibration TIMEOUT (0x5E, 0x80)
[ 6.071694] ad9361 spi32766.0: Calibration TIMEOUT (0x247, 0x2)
[ 6.827449] ad9361 spi32766.0: Calibration TIMEOUT (0x287, 0x2)
[ 7.055728] ad9361 spi32766.0: ad9361_probe : AD936x Rev 2 successfully initialized
[ 7.074192] cf_axi_dds 80004000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.00.b) at 0x80004000 mapped to 0xffffff8001310000, probed DDS AD9361
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[ 12.692196] cf_axi_adc 80000000.cf-ad9361-lpc: ADI AIM (10.00.b) at 0x80000000 mapped to 0xffffff8001318000, probed ADC AD9361 as MASTER
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1. I am using external clock of frequency 153.6 MHz and with dts of default parameters [apart from clock-frequency = <153600000>; in dts]. i am using fmcomms3 board + zcu102 dev board.

2. Calibration is timing out. Are other parameters [in dts] expected to changed or they WILL be automatically calculated by the device driver and applied?

3. ADC and DAC DMA drivers are tied to ad9361 init succcess?. i removed the external clock to board and the DDS and ADC were never init during bootup. so question is why are they tied to ad9361 init [is it because the DMA takes FRAME and CLKs from rfic ?].

4. can i control the init, reset, restart of ad9361 and DMAs from Application layer, assume i start using Libiio ?

 

Thanks

RC Reddy

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