We are trying to establish order of data that is transferred over JESD to an FPGA. We tried two tests:
one with User data and second one with captured analog data. We use predefined user pattern to tell us the order of data transferred over JESD. So our question is:
Is the order of JESD user pattern transfer the same order as the analog data transferred from ADC?
Here is my configuration: L=2, M=2, S=1, N'=16