I wonder how to synchronize the eight channels' sample data. When PGM is enable, after the ADC output 66A5, what the sample delay will be
This ADC only guarantees that channels will be synchronized to +/-1 clock cycle. Once the PGMx pin is driven low, the next packet will be valid data.
If you need sample clock synchronization, I recommend that you consider the AD9694 which employs the JESD204B serial standard including synchronization .
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