I am using the reference design daq2 2016_R2 with data rate 500MSPS for ADC and DAC. JESD link is working fine and I can pass the prbs tests. I can also generate the tone with the internal DDS.
When I trying to use the DMA, nothing works at all.
With the ILA, I can observe random data after the axi_ad9144_fifo. So I activated dac fifo by changing the constant to 1 in the HDL (the fifo is not bypassed). And I checked the box of the DMA to allow cyclic mode.
On the software side, I use this example (no-OS/dac_core.c at ecf8147b6e1c63fd649fea148482a6712d657a9c · analogdevicesinc/no-OS · GitHub ) to setup the DMA in cyclic mode and add
dmac_write(ad9144_dma, DMAC_REG_FLAGS, 0x1);
I set up a dual tone signal in a LUT that I send into the memory. The output of the DAC is then a multi-tone kind of noise signal. I cannot figure out where does the problem come from. The ILA shows that the output of the upack skip one sample (64bit) every couple of sample
On the ADC side, I can track the data with the ILA up to the input of the axi_ad9680_fifo, after the data are 0 so the memory is filled with 0.
Please, could you give me a tip? What am I doing wrong?
Thanks a lot for your help.