I am working on ad9361 , evaluation board Picozed-sdr2, NO-OS approach.
Based on my understanding, if I am to set the default_init_param.xo_disable_use_ext_refclk_enable = '1', I am using the 40MHz ref clk from an oscilllatoor on board the SOM.
How do I configure it to get the reference clock from connector J1 on the carrier card? I know I have to access the ad9361_clksel and set it HIGH to get its ref clk from connector J1 based on attachment pdf, pg 15.
Do you happen to have a api functions written inside for me to configure it?
Or I have to write my own api_function to access the AD9517 -3ABCPZ programmable clock synthesizer and the set the ad9361_clksel to HIGH?
And if I am to write my own api_function to access, is there any base configuration settings/callibrations I need to take note of, for example the tx/rx clk rate [bbpll, HB3, HB2, HB1, FIR,sampling rate .
Please kindly advise?