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What is the relationship between the SYNCC_CLK and the REF_CLK

Question asked by goddarduk on Mar 29, 2017
Latest reply on Mar 30, 2017 by KennyG

I'm proposing to use the AD9914 with a differential PECL REF_CLK of 1800MHz, the PLL being isolated. What I need to know is the mechanism by which the SYNC_CLK is generated from the REF_CLK, and by how much the REF_CLK jitter and phase noise is degraded at the SYNC_CLK output.

Thanks,

Doug Goddard

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