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axi_ad9361_dac_dma & axi_ad9361_adc_dma

Question asked by Selwyn on Mar 28, 2017
Latest reply on Apr 4, 2017 by rejeesh

Hi,

 

I would like to understand how these ip blocks works. There isn't much information online. I am trying to customize my own ip core to interface with the  ad9361 core , at the same time trying not to disturb/change the reference design as I do not want to affect the api functions that is interfacing these ip blocks so I can use the reference design as a base for my testing.

 

I tried to explore the .v files inside which is too much for me to understand. I also realized that there are 4 instantiated FIFO inside. Not sure what is does each of the individual FIFO do, what is their functionality  ? 

 

Does the functions in dac.c interface with the axi_ad9361_dac_dma ip block and ad9361 core ? Based on my understanding, it seems that the functions in dac.c: eg. dac_init has the options to choose whether to transmit via DDS or DMA. Correct me if I am wrong. And based on this link:

https://wiki.analog.com/resources/fpga/docs/axi_ad9361

It seems that there is more than 2 options which are pattern and prbs , does it mean that for the pattern and prbs we have to code ourselves? Dose the ad9361 core itself has the options for these 4 : DDS, DMA ,Patternn , PRBS, or is it just DDS and DMA options 

 

I am working on picosdr2 , using hdl_2015_r1 reference design.

 

Please kindly advise.

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