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HDL reference design register map

Question asked by oppradhan on Mar 28, 2017
Latest reply on Mar 29, 2017 by oppradhan

I was looking for the document/link that describes the register map for the DAC/ADC along with the associated DMA controller for my zynq + fmcomms1 based hardware. I can't seem seem to find the pdf that used to be previously accessible. The closest I can find is the webpage 'ADI Reference Designs HDL User Guide'.

Here is what I can't find

 

1. The section about 'Using and modifying the HDL designs' no longer describes the register maps.

 

2. If I try to look up the IP core section (to find info on the register maps and their descriptions) in this use guide then the AD9122 IP core is missing. Is the IP core for AD9144 the same? It seems like that is a quad DAC and so the IP core won't be directly mapped to the AD9122 core. 

 

3. Also there is no documentation about the axi DMA controller that is used in the logic chain, which I remember used to be there before.

 

4. What exactly is the purpose of the upack and pack IPs between the DMAC and the DAC/ADC IPs? These seem to be newer (post 2015) additions also. Are these configured in any way from the PS master? or the DMAC? The link for the util_upack IP core is broken and so I can't glean any info about this IP. Can you please look into fixing this or tell me about any alternative places that I can find the documentation resources for this?

 

5. It seems like between mid-2015 and the current releases the PL data chain has changed but the documentation is lacking describing each block, so that one can modify the design to ones own application.

 

 

 

 

I have an April 2015 revision pdf of the HDL reference user guide that contains the above information.  Seems like from the 'fmcomms1_bd.tcl' script the adi IP cores axi_9122, axi_dmac and axi_9643 are all still at version 1.0 in the master branch. So I assume this to mean that the HDL register map remains the same correct?

Still not able to figure out any details about the util_upack IP core.

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