I'm currently working with a FMCOMMS5 board on a ZC706. I've developed a new AXI module based on the existing AD9361 AXI module, with the intent to eventually have this new module leech off of the AD9361's output, do some data processing, and output the data in it's own data stream.
Anyways, I'm usually a high level programmer, so I apologize for my very limited knowledge when it comes to FPGA design. I'm trying to disable the data path so my module can get through the cf axi adc core initialization process without a DMA. From what I can tell, all I have to do is set the RO register "ADC_DP_DISABLE" to 1. My question is, how do I do this? I have the up_adc_common core in my AXI module, but it doesn't cover the 0x00C0 register (It only goes up to 0x002f from what I can see). Is there any examples I can follow that use this register? I'm guessing I don't want to edit the up_adc_common core. Should I simple create something similar to the up_adc_common core and have it respond to that specific register read request? Seems odd to me that it is missing that register.
I've also stumbled on the the fact that I can use the ID to skip the DMA initialization process, but I feel like if I'm going to continue to develop this core, I need to know the basics of how to implement this.
Any help would be greatly appreciated,