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ADRF6850's LOMON OUT have harmonics

Question asked by mzone on Mar 27, 2017
Latest reply on May 4, 2017 by mzone

pll

ADRF6850's LOMON out have harmonics every 500K as pic, I have changed the power supply from AC-DC to LDO ,and the 500K is like before. Does the ADRF6850 LOMON out always have the harmonics every 500K by itself or any other problem?

6850 LOMON OUT2

6850 LOMON OUT1

10M TCXO 1MPFD_0324.pll analysed at 03/28/17 14:01:47
 
PLL Chip is ADRF6850
Notes: 
VCO is ADRF6850
Reference is custom
 
VCO Divider Outside Loop: RFDIV = 001
 
Loop Filter designed at a VCO frequency of 3.52GHz with a Kv of 51.55MHz/V
 
Frequency Domain Analysis of PLL
  Analysis at PLL output frequency of 440MHz
 
Phase Noise Table 
Freq Total VCO Ref Chip SDM Filter
 100  -91.34  -122.7  -- -91.34  -194.9  -151.0 
1.00k -97.32  -119.2  -- -97.35  -154.9  -131.0 
10.0k -97.76  -117.2  -- -98.07  -114.1  -112.3 
 100k -78.66  -124.9  -- -102.6  -78.68  -112.2 
1.00M -141.1  -147.9  -- -146.9  -- -143.8 
 
Reference Spurious
  Noise and Jitter Calculations include the first 10 ref spurs
  First three spurs:  -300 dBc   -300 dBc   -300 dBc
 
Fractional-N Spur Estimate (worst case)
No significant spurs
 
Phase jitter using brick wall filter 
  from 10.0kHz to  100kHz
  Phase Jitter   1.68 degrees rms
 
ACP - Channel 1
  Channel 1 is centred 25.0kHz from carrier with bandwidth 15.0kHz
  Power in channel =  -52.0dBc
 
       ----    End of Frequency Domain Results   ----
 
Transient Analysis of PLL
  Power up transient to frequency of 450MHz
  Simulation run for  221us
 
Frequency Locking
  Time to lock to 1.00kHz is  204us
  Did not lock to within 10.0 Hz
 
Phase Locking (VCO Output Phase)
  Time to lock to 10.0 deg is  190us
  Time to lock to 1.00 deg is  213us
 
Lock Detect Threshold
  Time to lock detect exceeds 2.50 V is  182us
 
       ----    End of Time Domain Results   ----
 10M TCXO 1MPFD_0324.pll analysed at 03/28/17 14:01:47
 
PLL Chip is ADRF6850
Notes: 
VCO is ADRF6850
Reference is custom
 
VCO Divider Outside Loop: RFDIV = 001
 
Loop Filter designed at a VCO frequency of 3.52GHz with a Kv of 51.55MHz/V
 
Frequency Domain Analysis of PLL
  Analysis at PLL output frequency of 440MHz
 
Phase Noise Table 
Freq Total VCO Ref Chip SDM Filter
 100  -91.34  -122.7  -- -91.34  -194.9  -151.0 
1.00k -97.32  -119.2  -- -97.35  -154.9  -131.0 
10.0k -97.76  -117.2  -- -98.07  -114.1  -112.3 
 100k -78.66  -124.9  -- -102.6  -78.68  -112.2 
1.00M -141.1  -147.9  -- -146.9  -- -143.8 
 
Reference Spurious
  Noise and Jitter Calculations include the first 10 ref spurs
  First three spurs:  -300 dBc   -300 dBc   -300 dBc
 
Fractional-N Spur Estimate (worst case)
No significant spurs
 
Phase jitter using brick wall filter 
  from 10.0kHz to  100kHz
  Phase Jitter   1.68 degrees rms
 
ACP - Channel 1
  Channel 1 is centred 25.0kHz from carrier with bandwidth 15.0kHz
  Power in channel =  -52.0dBc
 
       ----    End of Frequency Domain Results   ----
 
Transient Analysis of PLL
  Power up transient to frequency of 450MHz
  Simulation run for  221us
 
Frequency Locking
  Time to lock to 1.00kHz is  204us
  Did not lock to within 10.0 Hz
 
Phase Locking (VCO Output Phase)
  Time to lock to 10.0 deg is  190us
  Time to lock to 1.00 deg is  213us
 
Lock Detect Threshold
  Time to lock detect exceeds 2.50 V is  182us
 
       ----    End of Time Domain Results   ----
 10M TCXO 1MPFD_0324.pll analysed at 03/28/17 14:01:47
 
PLL Chip is ADRF6850
Notes: 
VCO is ADRF6850
Reference is custom
 
VCO Divider Outside Loop: RFDIV = 001
 
Loop Filter designed at a VCO frequency of 3.52GHz with a Kv of 51.55MHz/V
 
Frequency Domain Analysis of PLL
  Analysis at PLL output frequency of 440MHz
 
Phase Noise Table 
Freq Total VCO Ref Chip SDM Filter
 100  -91.34  -122.7  -- -91.34  -194.9  -151.0 
1.00k -97.32  -119.2  -- -97.35  -154.9  -131.0 
10.0k -97.76  -117.2  -- -98.07  -114.1  -112.3 
 100k -78.66  -124.9  -- -102.6  -78.68  -112.2 
1.00M -141.1  -147.9  -- -146.9  -- -143.8 
 
Reference Spurious
  Noise and Jitter Calculations include the first 10 ref spurs
  First three spurs:  -300 dBc   -300 dBc   -300 dBc
 
Fractional-N Spur Estimate (worst case)
No significant spurs
 
Phase jitter using brick wall filter 
  from 10.0kHz to  100kHz
  Phase Jitter   1.68 degrees rms
 
ACP - Channel 1
  Channel 1 is centred 25.0kHz from carrier with bandwidth 15.0kHz
  Power in channel =  -52.0dBc
 
       ----    End of Frequency Domain Results   ----
 
Transient Analysis of PLL
  Power up transient to frequency of 450MHz
  Simulation run for  221us
 
Frequency Locking
  Time to lock to 1.00kHz is  204us
  Did not lock to within 10.0 Hz
 
Phase Locking (VCO Output Phase)
  Time to lock to 10.0 deg is  190us
  Time to lock to 1.00 deg is  213us
 
Lock Detect Threshold
  Time to lock detect exceeds 2.50 V is  182us
 
       ----    End of Time Domain Results   ----
 

 

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Moderator's Note:  Changed title and text from 'ADRF9850' to 'ADRF6850'

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