AnsweredAssumed Answered

Color depth problem with ADV7612+ADV7511

Question asked by linkwind on Mar 27, 2017
Latest reply on Mar 30, 2017 by linkwind

Dear ADI engineers,

 

    I got a problem in color depth in my design which use ADV7612 as a receiver and use ADV7511 as a Transmitter on it.

ADV7612's output is directly connected to ADV7511's input. Detail as below:

 

1.I configured the two chips according to 'ADV7612-VER.3.0c.txt' script, partially changed to use RGB 444  and colorspace 0~255.

 

problem is that:    

 I used the EDID from  'ADV7612-VER.3.0c.txt' script , and sent test pictures from PC through HDMI to  adv7612,

when the test pictures' color depth from 1~16, ADV7612's output for R/G/B have no change, the lowest four bits data for each color keep high.  The ADV7511 's output is correct.

 

Then , I tryied to use another edid according to VESA standard, ADV7612's output colorspace can be correct, but the ADV7511's output limited to 16~235.

 

So puzzled !!  Need your help, please!   Thanks.

 

 

my configuration:

 

adv_i2c_write(0x98, 0xFF, 0x80); //I2C Reset
adv_i2c_write(0x98, 0xF4, 0x80); //Config CEC slave address
adv_i2c_write(0x98, 0xF5, 0x7C); //Config INFOFRAME slave address

adv_i2c_write(0x98, 0xF8, 0x4C); //Config DPLL slave address
adv_i2c_write(0x98, 0xF9, 0x64); //Config KSV slave address
adv_i2c_write(0x98, 0xFA, 0x6C); //Config EDID slave address
adv_i2c_write(0x98, 0xFB, 0x68); //Config HDMI slave address
adv_i2c_write(0x98, 0xFD, 0x44); //Config CP slave address
adv_i2c_write(0x98, 0x01, 0x06); //Prim_mode = 110b HDI-GR
adv_i2c_write(0x98, 0x02, 0xF2); //Auto CSC, RGB out, Set RGB full grade 0-255 ,change
adv_i2c_write(0x98, 0x03, 0x40); //24 bit SDR 444 Mode 0
adv_i2c_write(0x98, 0x05, 0x28); //AV Codes Off
adv_i2c_write(0x98, 0x06, 0xA2); //Invert on VS,HS pins
adv_i2c_write(0x98, 0x0B, 0x44); //Power up part
adv_i2c_write(0x98, 0x0C, 0x62); //Power up part //off 0x66
adv_i2c_write(0x98, 0x14, 0x7F); //Max Drive Strength
adv_i2c_write(0x98, 0x15, 0x80); //Disable Tristate of Pins
adv_i2c_write(0x98, 0x19, 0x80); //LLC DLL phase(0-31,set 0)
adv_i2c_write(0x98, 0x33, 0x40); //LLD DLL MUX enable
adv_i2c_write(0x44, 0xBA, 0x00); //Set HDMI freerun //0x00
adv_i2c_write(0x64, 0x40, 0x81); //Disable HDCP 1.1 features

adv_i2c_write(0x68, 0x9B, 0x03); // ADI recommended setting
adv_i2c_write(0x68, 0x00, 0x01); //Set HDMI Input Port B (BG_MEAS_PORT_SEL = 000b)
adv_i2c_write(0x68, 0x02, 0x00); //Enable Ports A & B in background mode
adv_i2c_write(0x68, 0x83, 0xFC); //Enable clock terminators for port A & B
adv_i2c_write(0x68, 0x6F, 0x0C); //ADI recommended setting
adv_i2c_write(0x68, 0x85, 0x1F); //ADI recommended setting
adv_i2c_write(0x68, 0x87, 0x70); //ADI recommended setting
adv_i2c_write(0x68, 0x8D, 0x04); //LFG Port A
adv_i2c_write(0x68, 0x8E, 0x1E); //HFG Port A
adv_i2c_write(0x68, 0x1A, 0x8A); //unmute audio
adv_i2c_write(0x68, 0x57, 0xDA); //ADI recommended setting
adv_i2c_write(0x68, 0x58, 0x01); //ADI recommended setting
adv_i2c_write(0x68, 0x03, 0x98); //DIS_I2C_ZERO_COMPR
adv_i2c_write(0x68, 0x75, 0x10); //DDC drive strength
adv_i2c_write(0x68, 0x90, 0x04); //LFG Port B
adv_i2c_write(0x68, 0x91, 0x1E); //HFG Port B

adv_i2c_write(0x72, 0x01, 0x00); //Set N Value(6144)
adv_i2c_write(0x72, 0x02, 0x18); //Set N Value(6144)
adv_i2c_write(0x72, 0x03, 0x00); //Set N Value(6144)
adv_i2c_write(0x72, 0x15, 0x20); //Input 444(RGB or YCrCb) with Separate Syncs, 48k(High 4 bit--audio,Low 4 bit --video)
adv_i2c_write(0x72, 0x16, 0x30); //Output format 444, 24-bit RGB input
adv_i2c_write(0x72, 0x18, 0x46); //CSC disabled
adv_i2c_write(0x72, 0x40, 0x80); //General Control Packet Enable
adv_i2c_write(0x72, 0x41, 0x10); //Power Down control
adv_i2c_write(0x72, 0x48, 0x08); //Data right justified
adv_i2c_write(0x72, 0x49, 0x00); //No truncation
adv_i2c_write(0x72, 0x4C, 0x04); //8bit Output
adv_i2c_write(0x72, 0x55, 0x00); //Set RGB 444 in AVinfo Frame
adv_i2c_write(0x72, 0x56, 0x08); //Set active format Aspect
adv_i2c_write(0x72, 0x96, 0x20); //HPD Interrupt clear
adv_i2c_write(0x72, 0x98, 0x03); //ADI reqired write
adv_i2c_write(0x72, 0x99, 0x02); //ADI Required Write
adv_i2c_write(0x72, 0x9C, 0x30); //PLL Filter R1 Value
adv_i2c_write(0x72, 0x9D, 0x61); //Set clock divide
adv_i2c_write(0x72, 0xA2, 0xA4); //ADI Recommended Write
adv_i2c_write(0x72, 0xA3, 0xA4); //ADI Recommended Write
adv_i2c_write(0x72, 0xA5, 0x04); //ADI Recommended Write
adv_i2c_write(0x72, 0xAB, 0x40); //ADI Recommended Write
adv_i2c_write(0x72, 0xAF, 0x16); //Set HDMI Mode
adv_i2c_write(0x72, 0xBA, 0x60); //No clock delay
adv_i2c_write(0x72, 0xD1, 0xFF); //ADI Recommended Write
adv_i2c_write(0x72, 0xDE, 0xD8); //ADI Recommended Write
adv_i2c_write(0x72, 0xE4, 0x60); //VCO Swing Reference Voltage
adv_i2c_write(0x72, 0xFA, 0x7D); //Nbr of times to search for good phase
adv_i2c_write(0x72, 0xD6, 0xC0); //HPD always on

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