I have used AD9957 at single tone mode to output 50M signal(DDS),but there isn't single.Please help me,thanks
The problem appears to be the output amplitude setting. There are two ways to control the output amplitude in Single-Tone mode: 1) via OSK control, 2) via profile control.
The screen shot you provided indicates you are using OSK control. However, the amplitude setting indicates 0.00342, which is an extremely small signal. You will have great difficulty detecting this level on an oscilloscope. You might see it on a spectrum analyzer, but it will be very small (approx. -50dB). Change the amplitude to 1.000. This will provide a full scale output signal, which should easily show up on an oscilloscope or spectrum analyzer.
Alternatively, you can activate the Enable Profile ASF button on the Control window. This will make available the Amplitude SF edit boxes in the Profiles window. Setting the amplitude to 1.000 will provide a full scale output signal.
Thank you very much! But I have another question,PLL can't lock.Can you help me have a look ?
I hope to receive your reply as soon as possible.Because I am very worry.Thanks again.
I do not see anything fundamentally wrong with your setup.
The simplest check of device operation is to probe the SYNC_CLK pin. Assuming the SYNC_CLK output is enabled (which it is according to the programming setup you posted), it exhibits a divide-by-4 version of the internal system clock. So, if the PLL is running at all, you should see a clock signal at the SYNC_CLK pin with a frequency of 1/4th of the PLL's output frequency.
My only other suggestion is to use VCO1 instead of VCO0. There is a slight chance that 480 MHz is outside VCO0's frequency range (per Fig. 50 in the data sheet). Though this would only be the case if the particular device you have happens to be one that falls near one of the extremes of the silicon production process.
Thank you very much!
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