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Variable delay line for HMC661 and high speed ADC

Question asked by Lingmei on Mar 24, 2017
Latest reply on Apr 9, 2017 by Lingmei


I am planning to use HMC661 and a high speed ADC to capture a ultra narrow pulse (BW>10GHz). I notice that in a document for a similar device ( ), a variable delay line is suggested to set phase between the clock to the track-and-hold amplifier and the ADC so the ADC samples the hold-mode portion of the signal. Can anyone suggest a suitable variable delay line? The sampling rate we plan to use is 2GSPS or 2.5GSPS. Your help is appreciated, thanks!